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    • 专利摘要:
    A semiconductor device having a bipolar transistor capable of having a high degree of integration and a semiconductor device in which the bipolar transistor has good characteristic characteristics are described. The processing method for manufacturing the semiconductor device is described. The method of processing is a semiconductor through an opening formed in an insulating film in a portion covering a base region between an emitter and a collector and connected to the base of a lateral bipolar transistor. Forming an electrode layer connected to the base; Forming an insulating film from the same insulating film that covers the side wall next to the gate electrode of the MOS transistor and the base region between the emitter and the collector of the transverse bipolar transistor; Forming a gate electrode of the MOS transistor; Forming an insulating layer over the entire surface; Operating with a mask to form a layer covering a base region between the emitter and the collector of the lateral bipolar transistor; And etching the insulating film, thereby forming side walls for the gate electrode.
    公开号:KR20020006470A
    申请号:KR1020010041518
    申请日:2001-07-11
    公开日:2002-01-19
    发明作者:아라이치히로
    申请人:이데이 노부유끼；소니 가부시끼 가이샤；
    IPC主号:
    专利说明:

    Semiconductor device and manufacturing method therefor {Semiconductor device and production}
    [28] The present invention relates to a semiconductor device composed of a bipolar transistor and a processing method for manufacturing the same.
    [29] There is a semiconductor device called BiCMOS composed of a bipolar transistor and a CMOS transistor formed on a common substrate. This is due to the accurate analog processing and fast operation of bipolar transistors and the high integration and low power consumption of CMOS transistors.
    [30] When the MOS transistor is a LDD (Lightly Doped Drain) structure, the gate electrode has sidewalls formed on the side, and the LDD region is formed by introducing impurities using the gate electrode as a mask, and the source / drain region is It is formed by introducing impurities using the gate electrode and the side wall as a mask.
    [31] Incidentally, the LDD region is characterized by bringing a region in which the MOS transistor is lightly doped to the drain region, thereby reducing the field effect resulting from the reduced gate length while reducing the gate length.
    [32] In the case of the BiCMOS semiconductor device described above, the LDD structure can be formed in the same manner as described above when the MOS transistor has an LDD structure.
    [33] Examples of BiCMOS semiconductor devices are described next with reference to Figs. 16A and 16B, which are cross-sectional views showing structures observed after the side walls are formed in the fabrication processing step.
    [34] 16A is a cross-sectional view showing a PMOS transistor, an NMOS transistor, and a vertical NPN bipolar transistor (hereinafter simply referred to as NPN transistor). 16B is a cross-sectional view showing a lateral PNP transistor (hereinafter simply referred to as LPNP).
    [35] As shown in FIGS. 16A and 16B, the BiCMOS semiconductor device is composed of a PMOS transistor 101, an NMOS transistor 102, an NPN transistor 103, and an LPNP transistor 104.
    [36] An N + buried region 112 for the PMOS transistor 101, the NPN transistor 103, and the LPNP transistor 104 is formed in the P-type semiconductor substrate 111. An N-type epitaxial layer 113 is also formed on the semiconductor substrate 111. These components make up the semiconductor base 110.
    [37] The device insulating layer 115 is formed on the surface of the semiconductor base 110 by LOCOS, and the devices are insulated from each other.
    [38] In addition, the heavily doped N-type region 116 is formed to be connected to the collector of the NPN transistor 103 and the base of the LPNP transistor 104.
    [39] An N-type semiconductor well region 117 is formed in the PMOS transistor 101. The NMOS transistor 102 is formed with a P-type semiconductor well region 118W for the bipolar transistor and a P-type impurity region 118 operating as a channel stop region 118C.
    [40] In the semiconductor base 110, a gate oxide film 119 is formed for each of the PMOS and NMOS transistors 101 and 102. The gate oxide film 119 is formed with a gate electrode G of a tungsten polycide composed of an N-type polysilicon film 120 and a tungsten film 121.
    [41] The P-type LDD region 124 is formed in a portion of the N-type semiconductor region 117 adjacent to both sides of the gate electrode G of the PMOS transistor 101.
    [42] Similarly, LDD region 125 is formed in NMOS transistor 102.
    [43] In addition, the gate electrode G of each of the PMOS and NMOS transistors 101, 102 has an insulating side wall 128 that determines the width of the LDD regions 124, 125 on its side.
    [44] These sidewalls 128 are formed by coating the entire surface with an insulating film, and then performing reactive ion etching (RIE) on the insulating film.
    [45] When such reactive ion etching is performed to form the side wall 128, the epitaxial layer 113, which is silicon, is exposed except for the portion covered with the device insulating layer 115 and the polysilicon region (or gate electrode G). Therefore, RIE damages the silicon.
    [46] Problems arise in the process of manufacturing a silicon semiconductor device having a MOS transistor.
    [47] In the case of MOS transistors, the epitaxial layer (silicon) region that exposes itself when the sidewalls are formed is the source / drain region.
    [48] Since the source / drain regions are heavily doped, damage to the RIE only slightly affects transistor characteristics.
    [49] However, in the case of the BiCMOS semiconductor device shown in Figs. 16A and 16B, since the bipolar transistors 103 and 104 are formed in the region where silicon exposes itself, damage due to RIE greatly affects transistor characteristics. This is especially true for lateral bipolar transistors 104 formed near the surface of the semiconductor base. As a result, the surface recombination current is increased, and then the current amplification coefficient h FE at low power is reduced, so that the reliability is poor.
    [50] Therefore, in BiCMOS semiconductor devices it is important that the bipolar transistors, especially their active regions, are not damaged by RIE.
    [51] On the other hand, the lateral bipolar transistor is formed in such a manner that the regions of the emitter, the base, and the collector are diffused in the lateral direction. As a result, it has a larger area than a vertical bipolar transistor.
    [52] In order to increase the degree of integration of the semiconductor device, it is desirable to reduce the area for the lateral bipolar transistor.
    [53] (Summary of invention)
    [54] The present invention has been completed in view of the above. It is an object of the present invention to provide a semiconductor device composed of lateral bipolar transistors capable of high integration.
    [55] Another object of the present invention is to provide a semiconductor device composed of lateral bipolar transistors having good characteristics, and to provide a process for manufacturing the semiconductor device.
    [56] The present invention relates to a semiconductor device having a lateral bipolar transistor formed in a semiconductor base, wherein an opening is formed in an insulating film on the semiconductor base at a base connection portion of the lateral bipolar transistor, and through the opening. The electrode of the base connection portion is formed to be connected to the semiconductor base to cover the base region between the emitter and the collector.
    [57] The semiconductor device of the present invention configured as described above provides the advantage that the base connecting portion is formed in the region between the emitter and the collector. This structure makes it possible to reduce the cell size of the lateral bipolar transistor and reduce the parasitic capacity.
    [58] In addition, the semiconductor device constructed as described above provides the advantage that the emitter region and the collector region can be formed on both sides of the base region by a self-alignment process using the electrode layer of the base connection portion. . In other words, the base width is determined by self alignment, which results in stable characteristics. In addition, self alignment makes it possible to form the emitter region, the base region, and the collector region close to each other, which helps to reduce the cell size.
    [59] The present invention also provides a common insulating film in which a lateral bipolar transistor and a MOS transistor are formed on a common semiconductor base, and an insulating film covering the side wall on the gate electrode of the MOS transistor and the base region of the base connection portion of the lateral bipolar transistor is a common insulating film. It relates to a semiconductor device characterized in that it is formed.
    [60] An advantage of the semiconductor device constructed as described above is that an insulating film covering the base area of the base connection portion of the lateral bipolar transistor protects the base area.
    [61] Another advantage is that it is possible to form an insulating film covering the side wall and the base region on the gate electrode of the MOS transistor by a single process (since they are formed of a common insulating film). The insulating film protects the base region (which is the active region of the lateral bipolar transistor) from damage when etching is performed to form the side wall of the MOS transistor.
    [62] The present invention relates to a process for fabricating a semiconductor device having a MOS transistor and a lateral bipolar transistor formed on a common semiconductor base, which comprises forming a gate electrode of the MOS transistor, forming an insulating film on the entire surface, Forming a layer acting as a mask layer covering the base region between the emitter and the collector of the lateral bipolar transistor, and etching the insulating film to thereby form a sidewall of the gate electrode. do.
    [63] The above-described process has a step of forming a layer that acts as a mask layer covering the base region between the emitter and the collector of the lateral bipolar transistor. This mask layer protects the base region between the emitter and the collector, which is an active region of the lateral bipolar transistor, from damage by etching when etching is performed in the insulating film to form the side wall of the gate electrode.
    [1] 1 is a cross-sectional view showing the structure of a semiconductor device according to one embodiment of the present invention.
    [2] 2 is a cross-sectional view showing the structure of a semiconductor device according to one embodiment of the present invention.
    [3] 3A and 3B illustrate the steps of fabricating the semiconductor device shown in FIGS. 1 and 2.
    [4] 4A and 4B show steps for manufacturing the semiconductor device shown in FIGS. 1 and 2.
    [5] 5A and 5B illustrate the steps of fabricating the semiconductor device shown in FIGS. 1 and 2.
    [6] 6A and 6B illustrate the steps of fabricating the semiconductor device shown in FIGS. 1 and 2.
    [7] 7A and 7B illustrate steps for manufacturing the semiconductor device shown in FIGS. 1 and 2.
    [8] 8A and 8B show steps for manufacturing the semiconductor device shown in FIGS. 1 and 2.
    [9] 9A and 9B are sectional views showing the structure of a semiconductor device according to still another embodiment of the present invention.
    [10] 10A and 10B illustrate steps for manufacturing the semiconductor device shown in FIGS. 9A and 9B.
    [11] 11A and 11B show steps for manufacturing the semiconductor device shown in FIGS. 9A and 9B.
    [12] 12A and 12B show steps for manufacturing the semiconductor device shown in FIGS. 9A and 9B.
    [13] 13A and 13B illustrate steps of manufacturing the semiconductor device shown in FIGS. 9A and 9B.
    [14] 14A and 14B show steps for manufacturing the semiconductor device shown in FIGS. 9A and 9B.
    [15] 15A and 15B show steps for manufacturing the semiconductor device shown in FIGS. 9A and 9B.
    [16] 16A and 16B are sectional views showing the structure of a conventional BiCMOS semiconductor device taken immediately after the side walls are formed.
    [17] Explanation of symbols on the main parts of the drawings
    [18] 1, 101; PMOS transistors 2, 102; NMOS transistor
    [19] 3, 103; Vertical NPN Transistor
    [20] 4, 104; Transverse LPNP Transistor
    [21] 10, 110; Semiconductor bases 11, 111; P-type semiconductor substrate
    [22] 12, 112; N + buried regions 13, 113; N-type epitaxial layer
    [23] 15; Device isolation layer 115; Device insulation layer
    [24] 16, 116; N-type region 17, 117; N-type semiconductor well region
    [25] 18, 118; P-type impurity regions 19 and 119; Gate oxide
    [26] 23, 124, 125; LDD region 28, 128; Side wall
    [27] 31; Antireflection film
    [64] The present invention includes a semiconductor device having a lateral bipolar transistor formed in a semiconductor base, wherein an opening is formed in an insulating film on the semiconductor base at a base connection portion of the lateral bipolar transistor. And an electrode of the base connection portion is formed to be connected to the semiconductor base through the opening to cover the base region between the emitter and the collector.
    [65] According to the present invention, the above-described semiconductor device is characterized in that the vertical bipolar transistor is additionally formed in the semiconductor base, and the electrode of the base connection portion covering the base region of the transverse bipolar transistor and the emitter electrode of the vertical transistor are common It is configured to be formed from a layer.
    [66] According to the present invention, the aforementioned semiconductor device is configured such that an antireflection film is formed in the electrode layer of the base connecting portion.
    [67] According to the present invention, a lateral bipolar transistor and a MOS transistor are formed on a common semiconductor base, and sidewalls on the gate electrode of the MOS transistor and an insulating film covering the base region of the base connection portion of the lateral bipolar transistor are formed of a common insulating film. It includes a semiconductor device characterized in that.
    [68] According to the present invention, in the above-described semiconductor device, in the base connection portion of the lateral bipolar transistor, the electrode layer of the base connection portion is connected to the semiconductor base through an opening formed in the insulating film of the semiconductor base, and the base region between the emitter and the collector is connected. It is configured to cover.
    [69] According to the present invention, the semiconductor device described above is configured such that the vertical bipolar transistor is additionally formed in the semiconductor base, and the electrode layer of the base connection portion covering the base region and the emitter electrode of the vertical transistor are formed of a common layer. .
    [70] According to the present invention, the above-described semiconductor device is configured such that an antireflection film is formed in the electrode layer of the base connection portion.
    [71] The present invention includes a process for fabricating a semiconductor device having a MOS transistor and a lateral bipolar transistor formed on a common semiconductor base, which includes forming a gate electrode of the MOS transistor, forming an insulating film on the entire surface, Forming a layer acting as a mask layer covering the base region between the emitter and the collector of the lateral bipolar transistor, and etching the insulating film to thereby form a sidewall of the gate electrode. do.
    [72] According to the present invention, the above-described process for fabricating a semiconductor device is modified such that the step of forming a layer to be a mask layer forms an electrode layer for the base connection portion of the lateral bipolar transistor.
    [73] According to the present invention, the above-described process for fabricating a semiconductor device introduces impurities to form the emitter region and the collector region of the lateral bipolar transistor by a self-alignment process using a mask layer. It further comprises the step.
    [74] According to the present invention, the above-described process for fabricating a semiconductor device includes forming an antireflection layer on the topmost layer of the mask layer, and then introducing impurities to form the emitter region and the collector region of the lateral bipolar transistor. It includes more.
    [75] 1 and 2 are cross-sectional views illustrating BiCMOS semiconductor devices according to one embodiment of the present invention.
    [76] BiCMOS semiconductor devices consist of two sections. The first section includes a PMOS transistor, an NMOS transistor, and a vertical NPN bipolar transistor as shown in FIG. The second section includes a lateral PNP bipolar transistor.
    [77] As shown in Figs. 1 and 2, this BiCMOS semiconductor device is composed of a semiconductor base 10 and a transistor formed thereon. The semiconductor base 10 is composed of a P-type silicon substrate 11 and an N-type silicon epitaxial layer 13 formed thereon. The transistor includes a PMOS transistor 1, an NMOS transistor 2, a vertical NPN transistor 3 (hereinafter briefly NPN transistor), and a transverse NPN bipolar transistor 4 (hereinafter briefly LPNP transistor).
    [78] In the semiconductor base 10, an element insulating layer 15 is formed to isolate the transistors 1 to 4 from each other by LOCOS.
    [79] The PMOS transistor 1 includes an N + type buried region 12 formed in the semiconductor base 10 and an N type semiconductor well region 17 formed on the surface thereof.
    [80] P + type source / drain regions 33 are formed in the N-type semiconductor well region 17. In the source / drain regions 33, LDD regions 23 lightly doped to form P (adjacent to the channel) are formed.
    [81] On the channel, a gate oxide film 19 is interposed therebetween to form a gate electrode 22 having a laminated structure composed of a polysilicon film 20 and a tungsten film 21.
    [82] Side walls 28 of the insulating film are formed on the side of the gate electrode 22. The width of the sidewalls determines the width of the LDD region 23.
    [83] The wirings 44 and 45 of aluminum are connected to the source / drain region 33 through a tungsten plug layer 43.
    [84] The NMOS transistor 2 has a P-type semiconductor well region 18W formed in the semiconductor base 10.
    [85] An N + type source / drain region 34 is formed in this P-type semiconductor well region 18W. In the source / drain region 34, an LDD region 24 lightly doped to form N (adjacent to the channel) is formed.
    [86] On the channel, a gate oxide film 19 is interposed therebetween to form a gate electrode 22 having a laminated structure composed of a polysilicon film 20 and a tungsten film 21.
    [87] Side walls 28 of the insulating film are formed on the side of the gate electrode 22. The width of the sidewalls 28 determines the width of the LDD 24 region.
    [88] The wirings 46 and 47 of aluminum are connected to the source / drain region 34 through a plug layer 43 of tungsten.
    [89] Incidentally, a P-type impurity region 18 constituting the P-type semiconductor well region 18W is also formed between the NPN transistor 3 and the LPNP transistor 4. It also acts as channel stop region 18C, which isolates each other.
    [90] The vertical NPN bipolar transistor (NPN transistor) 3 has an N − type buried region 12 formed in the semiconductor base 10 composed of the silicon substrate 11 and the N type epitaxial layer 13.
    [91] The N-type epitaxial layer 13 includes a P-type base region (original base region and a link base region) 25 and a graft base region 33, and also an N + type emitter region 26. Is formed.
    [92] A collector connection region 16 heavily doped with N-type impurities is formed in the collector connection portion to be connected to the N + type buried region 12. The collector connection portion, which is a heavily doped N-type impurity region 34, is formed on the surface of the collector connection region 16.
    [93] The emitter electrode 26 of the polysilicon film 30 is connected to the emitter region 26.
    [94] Aluminum electrodes 48, 49, and 50 are respectively connected to the graft base region 33, the emitter electrode 30, and the collector connecting portion 34.
    [95] The bipolar transistor 3 constructed as described above is a vertical bipolar transistor of a polywashed emitter structure.
    [96] The transverse NPN bipolar transistor (LPNP transistor) 4 has an N + type buried region 12 formed in the semiconductor base 10 composed of the silicon substrate 11 and the N type epitaxial layer 13.
    [97] P + type emitter / collector regions 33 are formed in the N-type epitaxial layer 13.
    [98] In this way, the lateral bipolar transistor is formed such that the N-type epitaxial layer 13 operates as the base region and allows the movement of carriers in the vicinity of the surface.
    [99] An heavily doped N-type base connection region 16 is formed in the base connection portion to be connected to the N-type buried layer 12. The base connection portion of the heavily doped N-type impurity region 34 is formed on the surface of the base connection region 16.
    [100] The wires 60, 61, 62 of aluminum are connected to the emitter region 33, the collector region 33, and the base connecting portion 34 through the tungsten plug layer 43, respectively.
    [101] In this embodiment of the present invention, the LPNP transistor 4 is held between the emitter region 33 and the collector region 33 (with the N-type epitaxial layer 13 remaining on the surface of the semiconductor base 10). An insulating film 28 is formed so as to cover the portion to be formed, and the insulating film 28 is covered with the polysilicon film 30.
    [102] The insulating film 28 of the PMOS transistor 1 and the NMOS transistor 2 may be formed of the same material as that used as the side wall 28 on the side of the gate electrode 22.
    [103] In addition, the polysilicon film 30 may be formed of the same material as that used as the polysilicon film 30 of the emitter electrode in the NPN transistor 3.
    [104] In the source / drain region of the PMOS transistor 1 represented by the P-type impurity region 33, the graft base region of the NPN transistor 33, and the emitter / collector region of the LPNP transistor 4, the impurity concentration and the depth are all different. same.
    [105] The advantage of using the same film as the polysilicon film as the insulating film of another transistor is that they can be formed in a single processing process.
    [106] According to this embodiment of the present invention, the NPN transistor 3 and the LPNP transistor 4 are characterized in that the anti-reflection film 31 is formed on the polysilicon film 30.
    [107] The antireflection film 31 provides the following advantages in manufacturing.
    [108] (1) In the photolithography process in which the polysilicon film 30 forms a patterned resist film, the antireflection film 31 is exposed to light by the surface of the polysilicon film 30. To prevent reflection.
    [109] Reflection of the exposure light by the surface of the polysilicon film 3 causes the resist film to be exposed under conditions different from those designed, and as a result, the polysilicon film is not patterned as desired.
    [110] (2) In the ion implantation step using the polysilicon film 30 as a mask to form the impurity regions of the NPN transistor 3 and the LPNP transistor 4, the antireflection film 31 is made of polysilicon containing impurities due to ion implantation. Entry into the membrane 30 is prevented.
    [111] In the NPN transistor 3, the graft base region is P-type and the polysilicon film 30 of the emitter electrode is N-type so as to form the emitter region 26. As a result, the P-type impurity entering the polysilicon film 30 during the ion implantation to form the graft base region causes the P-type concentration in the polysilicon film 30 to vary, thereby causing the emitter region 26 to have a desired impurity concentration. Makes it impossible to form.
    [112] According to this embodiment of the present invention, in the LPNP transistor 4, the polysilicon film 30 on the left side of the emitter regions 33 and 33E is formed by the emitter regions 33 and 33E through the plug layer 43. It is configured to be connected to the wiring 60 which is connected to).
    [113] This structure allows the polysilicon film 30 to have the same potential as the emitter regions 33 and 33E, thereby preventing the polysilicon film 30 from having a floating potential.
    [114] Although the sectional view of FIG. 2 shows that the LPNP transistor 4 has a polysilicon film 30 formed at two separate positions, in practice, the polysilicon film 30 is formed so as to surround the emitter regions 33 and 33E. do.
    [115] Therefore, in FIG. 2, the two polysilicon films 30 are connected to each other so that the right polysilicon film 30 has the same potential as the emitter regions 33 and 33E.
    [116] This structure can be changed so that the polysilicon film 30 is connected to the wiring 61 of the collector regions 33 and 33C and has the same potential as the collector regions 33 and 33C.
    [117] The semiconductor device shown in Figs. 1 and 2 is fabricated by the process described later with reference to Figs. 3A to 8B.
    [118] The portion shown in FIG. 3A corresponds to the portion shown in FIG. 1. The part shown in FIG. 3B corresponds to the part shown in FIG. 2. The same correspondence applies to Figs. 4A to 8B.
    [119] First, a P-type silicon substrate 11 of the first conductivity type is prepared. See FIGS. 3A and 3B. The silicon substrate is subjected to a thermal oxidation treatment so that an oxide film (not shown) of 300 nm thickness is formed on the surface thereof.
    [120] The silicon substrate 11 is coated with a photoresist film and then patterned by lithography. The patterned resist film has openings at positions where the NPN transistor 3, the LPNP transistor 4, and the PMOS transistor 1 are to be formed on the silicon substrate 11.
    [121] Wet etching with hydrofluoric acid is performed on the oxide film formed on the silicon substrate 11 through a resist film which is an etching mask. Thus, openings are formed in the oxide film.
    [122] The photoresist film used as the etching mask is removed using a mixture of hydrogen peroxide and sulfuric acid.
    [123] Antimony diffuses into the silicon substrate 11 through the opening formed in the oxide film. This step is achieved by heating antimony oxide (Sb 2 O 3 ) at 1200 ° C. for 60 minutes. This thermal diffusion rises from the silicon substrate 11 to the buried region 12 of the second conductivity type (N type (N + type) in this embodiment).
    [124] An N-type buried region 12 is now formed at the position where the NPN transistor 3, the LPNP transistor 4, and the PMOS transistor 1 are to be formed.
    [125] Wet etching with hydrofluoric acid is performed to selectively remove the oxide film.
    [126] An N-type epitaxial layer 13 (1 μm thick and having a resistance of 1 Ωcm) is formed by epitaxy in the silicon substrate 11.
    [127] In this way, the semiconductor base 10 composed of the silicon substrate 11 and the N-type epitaxial layer 13 is obtained.
    [128] The device isolation layer 15 is formed on the N-type epitaxial layer 13 by LOCOS as follows.
    [129] The surface of the N-type epitaxial layer 13 is thermally oxidized to form a silicon oxide film 14 (30 nm thick). In the silicon oxide film 14, a silicon nitride film (not shown) of 100 nm thickness is formed by reduced pressure CVD. The silicon nitride film is selectively removed by reactive ion etching. A silicon nitride film used as an anti-oxidation mask to remain unetched, the surface of the N-type epitaxial layer 13 is thermally heated in a humid oxygen atmosphere of 1050 ° C. to form a device insulating layer 15 having a thickness of 450 nm. Is oxidized. The silicon nitride film is selectively removed by etching with hot phosphoric acid at 150 ° C.
    [130] The N-type region 16 connected to the buried region 12 is formed at the position where the NPN transistor 3 and the LPNP transistor are to be formed in the N-type epitaxial layer 13.
    [131] To form the N-type region 16, a resist film (not shown) having an opening is formed at the position where the N-type region 16 is to be formed. Using this resist film as an etching mask, doping of phosphorus by ion implantation of energy of 500 keV for a dose of 2 x 10 12 / cm 2 and 70 keV for a dose of 7 x 10 15 / cm 2 is achieved. Is executed.
    [132] The resist film used as the etching mask is removed in a general manner.
    [133] Subsequently, MOS transistors 1 and 2 are formed.
    [134] Some of the N-type epitaxial layer 13 on which the PMOS transistor 1 is to be formed has an energy of 600 keV for a dose of 5 x 10 12 / cm 2 and an energy of 300 keV for a dose of 3 x 10 12 / cm 2 . Phosphorus is doped by ion implantation of. In this way, the N-type semiconductor well region 17 is formed.
    [135] Doping of boron for Vth control is performed with ion implantation of energy of 20 keV for a dose of 5 x 10 12 / cm 2 .
    [136] Doping of boron (P-type impurity) is performed between a portion of the silicon substrate 11 and the N-type epitaxial layer 13 on which the NMOS transistor 2 is formed, and the portion on which the NPN transistor 3 and the LPNP transistor 4 are formed. It is carried out by ion implantation in a portion of the silicon substrate 11 and the N-type epitaxial layer 13 held at. Ion implantation is 5 x 10 of 800 keV for a dose of 12 / cm 2 of energy, 5 x 10 12 / cm of 100 keV for the 350 keV energy, and 5 x 10 12 / cm 2 dose to the dose of 2 Runs with energy In this way, regions 18 doped with P-type impurities that act as P-type semiconductor well regions 18 (18W) and channel stop regions 18 (18C) are formed.
    [137] Doping for Vth control is carried out with ion implantation of 20 keV of energy for a dose of 2 × 10 12 / cm 2 . The above steps are described with reference to FIGS. 3A and 3B.
    [138] The silicon oxide film 14 is removed by wet etching with hydrofluoric acid.
    [139] Oxidation is carried out at 850 ° C. for 5 minutes in a humid oxygen atmosphere.
    [140] In this way, a gate oxide film 19 (5 nm thick) is formed in the region except the device isolation layer 15.
    [141] The polysilicon film 20 (100 nm thick) to be a gate electrode is formed by low pressure CVD.
    [142] The polysilicon film 20 is heavily doped with phosphorus by previously depositing POCl 3 (phosphorus trichloride oxide).
    [143] The tungsten silicide film 21 (thickness of 100 nm) is formed by CVD. The tungsten silicide film 21 and the polysilicon film 20 are selectively removed except for the portions constituting the gate electrode of the MOS transistor by conventional lithography techniques and reactive ion etching.
    [144] In this way, a gate electrode 22 having a polycrystalline tungsten silicide structure composed of the polysilicon film 20 and the tungsten silicide film 21 is formed in the portion where the PMOS transistor 1 and the NMOS transistor 2 are formed. This step is described in Figures 4a and 4b.
    [145] In the portion where the PMOS transistor 1 is to be formed, doping of P-type impurities such as boron fluoride (BF 2 ) is performed by ion implantation of energy of 25 keV for a dose of 2 × 10 13 / cm 2 . This doping forms a P-type LDD region 23 in a portion of the N-type semiconductor well region 17 on both sides of the gate electrode 22.
    [146] In the portion where the NMOS transistor 2 is to be formed, doping of N-type impurities such as arsenic is performed by ion implantation of energy of 60 keV for a dose of 3.5 x 10 13 / cm 2 . This doping forms an N-type LDD region 24 in a portion of the P-type semiconductor well region 18W on both sides of the gate electrode 22.
    [147] In the portion where the NPN transistor 3 is to be formed, doping of P-type impurities such as boron fluoride is performed by ion implantation of energy of 30 keV for a dose of 5 x 10 13 / cm 2 . This doping forms the original base and link base regions 25.
    [148] Doping of an N-type impurity such as phosphorus is carried out with ion implantation of energy of 120 keV for a dose of 2 × 10 12 / cm 2 and 360 keV for a dose of 3 × 10 12 / cm 2 through the same opening. This step forms the SIC (Slective Ion Implantation of Collector) 27. This step is described in Figures 5a and 5b.
    [149] The region 25 operating as both the original base and the link base of the NPN bipolar transistor 3 is the same size (width) as the polysilicon film 30 (to be formed later) connected to the emitter.
    [150] The silicon oxide film 28 (200 nm thick) used to form the LDD is formed by CVD.
    [151] The opening 29 is formed by a conventional lithography technique and reactive ion etching in a part of the silicon oxide film 28 where the emitter of the NPN transistor 3 is to be formed.
    [152] The polysilicon film 30 (150 nm thick) heavily doped with arsenic (N-type impurity) is formed by CVD.
    [153] The antireflection film 31 is formed of a silicon oxide film (10 nm thick) formed by CVD and a silicon oxynitride film (110 nm thick) formed by CVD.
    [154] The entire surface is coated with a photoresist 32, which is then patterned with conventional lithography to cover the width of the emitter electrode (polysilicon film 30) of the NPN transistor 3 and the base of the LPNP transistor 4. Determine the width
    [155] Reactive ion etching using the photoresist 32 as a mask is performed to continuously pattern the antireflective film 31 and the polysilicon film 30. This step is described in Figures 6a and 6b.
    [156] The pattern distance of the polysilicon film 30 determines the base width of the LPNP transistor 4 shown in FIG. 6B.
    [157] Reactive ion etching using the photoresist 32 as a mask is performed on the silicon oxide film 28. Thus, sidewalls 28 are formed next to the gate electrodes 22 of the PMOS transistor 1 and the NMOS transistor 2.
    [158] Since the reactive ion etching is covered with the silicon oxide film 28 and the polysilicon film 30, the N-type epitaxial layer 13 serving as the base region layer of the LPNP transistor 4 is not damaged.
    [159] The photoresist 32 is then removed.
    [160] The LPNP transistor 4 is left with a silicon oxide film 28, a polysilicon film 30, and an antireflection film 31 covering a portion of the N-type epitaxial layer 13 to be a base region later. This step is described in Figures 7a and 7b.
    [161] A 10 nm thick silicon oxide film (not shown) is formed by CVD. It is grown to 12 nm by thermal oxidation.
    [162] Doping of N-type impurities such as arsenic causes ion implantation of 35 keV of energy for a dose of 5 x 10 15 / cm 2 in the region where the NMOS transistor 2, NPN transistor 3, and LPNP transistor 4 will be formed. Is executed.
    [163] Thus, an N-type impurity region 34 is formed which operates from the NMOS transistor 2 to the source / drain region, to the collector of the NPN transistor 3 and to the base of the LPNP transistor 4. .
    [164] Doping of P-type impurities such as boron fluoride is carried out with an energy of 35 keV for a dose of 3 x 10 15 / cm 2 in the region where the PMOS transistor 1, NPN transistor 3, and LPNP transistor 4 will be formed. do.
    [165] Thus, a P-type impurity that operates from the PMOS transistor 1 to the source / drain region, the graft base region of the NPN transistor 3, and the emitter region 33E / collector region 33C of the LPNP transistor 4 Region 33 is formed. This step is described in Figures 8a and 8b.
    [166] It should be noted that the graft base region of the NPN transistor 3 and the emitter / collector region of the LPNP transistor 4 are determined through self alignment by the polysilicon film 30 and the antireflection film 31.
    [167] Therefore, in the LPNP transistor 4, the emitter-collector distance is determined by the width of the polysilicon film 30.
    [168] The anti-reflection film 31 acts as a mask during the doping of the P-type impurity by ion implantation to form the graft base region of the NPN transistor 3 and the emitter / collector region of the LPNP transistor 4. Therefore, the antireflection film 31 protects the polysilicon film 30 from being doped with P-type impurities. The peak concentration of the P-type impurity is left in the antireflection film 31.
    [169] The above-described steps follow the conventional steps used in the fabrication of BiCMOS semiconductor devices.
    [170] For example, a wafer is subjected to heat treatment (or RTA = Rapid Thermal Annealing) at 1000 ° C. for 10 seconds to activate impurities. The wafer is then entirely coated with boron-phosphorus silicate glass (BPSG) to form the interlayer insulator 35. This step is followed by reflux in a nitrogen atmosphere for 20 minutes at 900 ° C. to smooth the surface of the interlayer insulator 35.
    [171] The listed openings (contact holes) are then made in the interlayer insulator 35. Each contact hole is a layer filled with a plug layer 43 for wiring connection.
    [172] The openings 36 and 37 reach the source / drain regions 33 of the PMOS transistor 1. Openings 38 and 39 reach the source / drain regions 34 of the NMOS transistor 2. The opening 40 reaches the outer base region 33 of the NPN transistor 3. The opening 41 reaches the polysilicon film 30 of the emitter electrode. The opening 42 leads to the heavily doped N-type region 34. The opening 52 leads to an electrode 30 connected to the base of the LPNP transistor 4. The opening 53 leads to the emitter region 33. The opening 54 reaches the collector region. The opening 55 leads to a portion 34 connected to the base.
    [173] Each opening 36 to 42 and 52 to 55 is filled with tungsten to form the plug layer 43 in a conventional manner, and the wiring to each portion is followed through the plug layer 43 by conventional wiring techniques. Are made together.
    [174] The wirings 44 and 45 are connected to the source / drain region 33 of the PMOS transistor 1. The wirings 46 and 47 are connected to the source / drain region 34 of the NMOS transistor 2. The wiring 48 is connected to the outer base region 33 of the NPN transistor 3. The wiring 49 is connected to the polysilicon film 30 of the emitter electrode of the NPN transistor 3. The wiring 50 is connected to the heavily doped N-type region 34 of the NPN transistor 3. The wiring 60 is connected to the emitter region 33E and the polysilicon film 30 of the LPNP transistor 4. The wiring 61 is connected to the collector region 33C of the LPNP transistor 4. The wiring 62 is connected to an area 34 connected to the base of the LPNP transistor 4.
    [175] Now a PMOS transistor 1, an NMOS transistor 2, an NPN bipolar transistor 3, and an LPNP transistor 4 are formed in the semiconductor base 10 to form a BiCMOS semiconductor device as shown in FIGS. 1 and 2. Is obtained.
    [176] An advantage of the above-described embodiment is that since the base region is covered with the silicon oxide film 28 and the polysilicon film 30, the surface of the base region 13 in the LPNP transistor 4 is protected from damage due to etching. .
    [177] Thus, it is possible to prevent the current amplification coefficient h FE at low current from decreasing when the surface recombination current is increased in the LPNP transistor 4.
    [178] This improves the reliability of the BiCMOS semiconductor device.
    [179] The polysilicon film 30 is used for self alignment when the heavily doped emitter regions and collector regions are formed in the LPNP transistor 4.
    [180] As a result, the heavily doped emitter regions and collector regions are formed on a part of the surface of the N-type epitaxial layer 13 which is not covered with the silicon oxide film 28 and the polysilicon film 30. Thus, the N-type epitaxial layer 13 almost retains its characteristic characteristics even if its surface is damaged by etching.
    [181] In addition, the structure described above allows the polysilicon film 30 to determine the emitter-collector distance.
    [182] Since the NPN transistor 3 is configured so that the N-type epitaxial layer 13 is covered with the silicon oxide film 28 and the polysilicon film 30, the surface of the base region 13 is protected from damage due to etching.
    [183] The polysilicon film 30 of the emitter electrode serves for self alignment when a heavily doped graft base is formed. Thus, the graft base region retains its characteristic properties almost intact even if its surface is damaged by etching.
    [184] The above described embodiment provides the following advantages.
    [185] The resist film can be patterned as desired due to exposure due to the antireflection film 31 formed in the polysilicon film 30 in the NPN transistor 3 and the LPNP transistor 4.
    [186] The anti-reflection film 31 protects the polysilicon film 30 from being doped with P-type impurities when ion implanted to form the P-type impurity region 33, and the peak concentration of impurities remains in the anti-reflection film 31. Lose.
    [187] The common insulating film is an insulating film 28 which is a side wall next to the electrode 22 in the MOS transistors 1 and 2, an insulating film 28 below the polysilicon film 30 of the emitter electrode in the NPN transistor 3, And an insulating film 28 covering the base region 13 between the emitter region and the collector region in the LPNP transistor 4. Therefore, these insulating films can be formed simultaneously by the same steps.
    [188] Similarly, a common insulating film covers the polysilicon film 30 of the emitter electrode of the NPN transistor 3 and the polysilicon film 30 covering the base region 13 between the collector region and the emitter region of the LPNP transistor 4. Configure Therefore, these polysilicon films can be formed simultaneously by the same steps.
    [189] The P-type impurity region 33 having the same impurity concentration and depth includes the source / drain region 33 of the PMOS transistor 1, the external base region of the NPN transistor 3, and the emitter region of the LPNP transistor 4 ( 33E) / collector region 33C. Therefore, these regions can be formed simultaneously by the same process.
    [190] The fact that one film of one transistor is the same as another film of another transistor means that they can be formed simultaneously by the same steps. This type of fabrication process requires fewer steps than forming each film. Thus, it is possible to fabricate an improved BiCMOS semiconductor device without increasing the number of fabrication steps.
    [191] The fact that the LPNP transistor 4 is configured such that the polysilicon film 30 (covering the base region 13 between the emitter region 33E and the collector region 33C) is connected to the wiring of the emitter region 33E. Allows the polysilicon film 30 to be maintained at the same potential as the emitter region 33E (or collector region 33C). This prevents the potential of the polysilicon film 30 from floating.
    [192] Next, a second embodiment of the present invention will be described.
    [193] This embodiment is characterized in that the lateral bipolar transistor is configured differently from the conventional so as to achieve a high degree of integration.
    [194] 9A and 9B are cross-sectional views showing BiCMOS semiconductor devices for a second embodiment of the present invention.
    [195] BiCMOS semiconductor devices are composed of PMOS transistors, NMOS transistors, vertical NPN bipolar transistors, and transverse PNP bipolar transistors. The first three are shown in FIG. 9A and the last one is shown in FIG. 9B.
    [196] 9A and 9B, the BiCMOS semiconductor device for the second embodiment is similar to that for the first embodiment (shown in FIGS. 1 and 2). The semiconductor base 10 (composed of the P-type silicon substrate 11 and the N-type silicon epitaxial layer 13 formed thereon), the PMOS transistor 1, the NMOS transistor 2, the vertical NPN bipolar transistor ( 3) (hereinafter simply NPN transistor), and transverse PNP bipolar transistor 5 (hereinafter briefly LPNP transistor).
    [197] The PMOS transistor 1, the NMOS transistor 2, and the NPN transistor 3 shown in FIG. 9A have the same structure as that shown in FIG.
    [198] The semiconductor device for this embodiment is characterized in that the LPNP transistor 5 shown in FIG. 9B is configured differently from the LPNP transistor 4 shown in FIG.
    [199] Specifically, the LPNP transistor 5 has an N-type semiconductor epitaxial layer (26), in which regions 26 and 26B connected to the N + base are formed between the P-type emitter region 33E and the P-type collector region 33C. 13).
    [200] In addition, regions 26 and 26B connected to the base are adjacent to the polysilicon film 30.
    [201] The polysilicon film 30 is adjacent to the silicon of the semiconductor base 10 through the opening 51 in the insulating film 28.
    [202] In addition, an anti-reflection film 31 is formed on the polysilicon film 30.
    [203] The width of the polysilicon film 30 connected to the base itself determines the emitter-collector distance.
    [204] In other words, the portion connected to the base in the LPNP transistor 5 is configured in the same way as the portion connected to the emitter in the NPN transistor 3.
    [205] This structure allows the portion connected to the base in the LPNP transistor 5 to be formed by the same steps at the same time as the portion connected to the emitter in the NPN transistor 3.
    [206] The fact that the LPNP transistor 5 is configured as described above allows the portion connected to the base to be formed between the emitter region and the collector region. As a result, the area occupied by the LPNP transistor 5 is reduced.
    [207] This is evident in comparison with the LPNP transistor 4 shown in FIG.
    [208] Incidentally, the polysilicon film 30 is not floating because it is connected to the wiring 64 connected to the base. This makes it unnecessary for the polysilicon film 30 to have the same potential as that of the emitter region 33E or the collector region 33C.
    [209] The structure other than that described above for the LPNP transistor 5 is the same as that of the LPNP transistor 4 shown in FIG. The description is not repeated.
    [210] The semiconductor device for the embodiment shown in FIGS. 9A and 9B is fabricated by the processing described below with reference to FIGS. 10A-15B.
    [211] The portion shown in FIG. 9A corresponds to the portion shown in FIG. 10A. The part shown in FIG. 9B corresponds to the part shown in FIG. 10B. The same correspondence as described above also applies to Figs. 11A to 15B.
    [212] The same steps as in the first embodiment are briefly described.
    [213] First, a silicon substrate 11 of the first conductivity type (P type in this embodiment) is prepared. In the silicon substrate 11, an N-type (N + ) buried region 12 is formed in a portion where the NPN transistor 3 is formed, a portion where the LPNP transistor 5 is formed, and a portion where the PMOS transistor 1 is formed. do.
    [214] An epitaxially formed N-type epitaxial layer 13 (1 μm thick and having a resistance of 1 Ωcm) is formed on the silicon substrate 11. Thus, the semiconductor base 10 composed of the silicon substrate 11 and the N-type epitaxial layer 13 is formed.
    [215] An element isolation layer 15 is formed in the N-type epitaxial layer 13 by LOCOS.
    [216] The heavily doped N-type region 16 connected to the buried region 12 is formed in the portion where the NPN transistor 3 is to be formed in the N-type epitaxial layer 13.
    [217] In this embodiment, the heavily doped N-type region 16 is not formed in the portion where the LPNP transistor 5 is to be formed.
    [218] The N type semiconductor well region 17 is formed in the portion where the PMOS transistor 1 is to be formed in the N type epitaxial layer 13.
    [219] The P-type doped region 18, which will later be a P-type semiconductor well region 18 (18W) and a channel stop region 18 (18C), has a portion where an NMOS transistor 2 is formed and an NPN transistor 3 is formed thereon. A portion is formed between the portion and the portion where the LPNP transistor 5 is to be formed. This step is described in FIGS. 10A and 10B.
    [220] The oxide film 14 is removed, and then a gate oxide film 19 is formed in the portion except the device isolation layer 15.
    [221] A polysilicon film 20 to be later formed as a gate electrode is formed, which is then heavily doped with phosphorus.
    [222] The tungsten silicide film 21 is formed in the polysilicon film 20.
    [223] The tungsten silicide film 21 and the polysilicon film 20 are selectively removed by etching except for the gate electrode of the MOS transistor. The gate electrode 22 composed of the polysilicon film 20 and the tungsten silicide film 21 is formed in the portion where the PMOS transistor 1 and the NMOS transistor 2 are to be formed. This step is described in Figures 11A and 11B.
    [224] The P-type LDD region 23 is formed in the portion where the PMOS transistor 1 is to be formed in the N-type semiconductor well region 17 on both sides of the gate electrode 22 by ion implantation.
    [225] The N-type LDD region 24 is formed in the portion where the NMOS transistor 2 is to be formed in the P-type semiconductor well region 18 on both sides of the gate electrode 22 by ion implantation.
    [226] The region 25 serving as the original base and the link base is formed in the portion where the NPN transistor 3 is to be formed by ion implantation into P-type impurities.
    [227] SIC 27 is formed by ion implantation into N-type impurities through the same opening. The above steps are described in FIGS. 12A and 12B.
    [228] The silicon oxide film 28 is formed on the entire surface. The opening 29 is formed in the portion of the silicon oxide film 28 that becomes the emitter of the NPN transistor 3.
    [229] At the same time as this step, an opening 51 is formed in the silicon oxide film 28 to be connected to the base of the LPNP transistor 5.
    [230] A polysilicon film 30 heavily doped with N-type impurities is formed on the entire surface. In the portion connected to the base of the LPNP transistor 5, the polysilicon film 30 is connected to the silicon of the semiconductor base 10 through the opening 51 formed in the insulating film 28.
    [231] The polysilicon film 30 is formed with an antireflection film 31 composed of a silicon oxide film and a silicon oxynitride film stacked thereon.
    [232] The surface is coated with a photoresist 32, which is subsequently patterned to determine the base width of the LPNP transistor 5.
    [233] Using the photoresist 32 as a mask, the anti-reflection film 31 and the polysilicon film 30 are subsequently subjected to reactive ion etching for patterning. This step is described in Figures 13A and 13B.
    [234] Using the photoresist 32 as a mask, reactive ion etching is performed on the silicon oxide film 28 to form sidewalls 28 on the side of the gate electrodes 22 and 23.
    [235] In this step for the LPNP transistor 5, the reactive ion etching is covered with the silicon oxide film 28 and the polysilicon film 30, so that the damage to the N-type epitaxial layer 13 in the base region is prevented. Does not cause
    [236] Subsequently, the photoresist 32 is removed.
    [237] In the LPNP transistor 5, the silicon oxide film 28, the polysilicon film 30, and the anti-reflection film 31 that cover the N-type epitaxial layer 13 are held in a portion to be a base region later. This step is described in Figures 14A and 14B.
    [238] A silicon oxide film (not shown) is formed by CVD and grown by thermal oxidation.
    [239] The region where the NMOS transistor 2 and the NPN transistor 3 are to be formed is doped with N-type impurities by ion implantation. The resulting N-type impurity region 34 is connected to the source / drain region of the NMOS transistor 2 and the collector of the NPN transistor 3.
    [240] Doping of the P-type impurity is performed by ion implantation in the region where the PMOS transistor 1, the NPN transistor 3, and the LPNP transistor 4 are to be formed. The resulting P-type impurity region 33 is the source / drain region of the PMOS transistor 1, the graft base region of the NPN transistor 3, and the emitter region 33E / collector region 33C of the LPNP transistor 5. Configure This step is described in Figures 15A and 15B.
    [241] The graft base region of the NPN transistor 3 and the emitter region 33E / collector region 33C of the LPNP transistor 5 are formed by the polysilicon film 30 and the anti-reflection film 31 disposed thereon in self alignment. Has a determined position.
    [242] Therefore, the emitter-collector distance in the LPNP transistor 5 is determined by the width of the polysilicon film 30.
    [243] The anti-reflection film 31 serves as a mask when doping P-type impurities by ion implantation to form the graft base region of the NPN transistor 3 and the emitter region 33E / collector region 33C of the LPNP transistor 5. It works. Therefore, the antireflection film 31 protects the polysilicon film 30 from the doping of P-type impurities. The peak concentration of the P-type impurity is left in the antireflection film 31.
    [244] The above-described steps follow the conventional steps used in the fabrication of BiCMOS semiconductor devices.
    [245] On the entire surface, an interlayer insulating film 35 of boron-phosphorus silicate glass (BPSG) is formed.
    [246] The openings (contact holes) listed thereafter are made in the interlayer insulating film 35. Each contact hole is later filled with a plug layer 43 for wiring connection.
    [247] Openings 36 and 37 are formed in the PMOS transistor 1. Openings 38 and 39 are formed in the NMOS transistor 2. Openings 40, 41, and 42 are formed in the NPN transistor 3. An opening to the emitter region 33 of the LPNP transistor 5 is formed. An opening 57 is formed that leads to the polysilicon region 30 of the electrode connected to the base. An opening 58 is formed to reach the collector region 33.
    [248] Each opening 36 to 42 and 56 to 58 is filled with tungsten to form the plug layer 43 in a conventional manner, and the wiring to each portion is through the plug layer 43 using conventional wiring techniques as follows. Is made.
    [249] The wirings 44, 45 of the PMOS transistor 1, the wirings 46, 47 of the NMOS transistor 2, and the wirings 48, 49, 50 of the NPN transistor 3 are formed. A wiring 64 for connecting to the polysilicon region 30 of the electrode connected to the base and a wiring 65 for connecting to the collector region 33 are formed.
    [250] A PMOS transistor 1, an NMOS transistor 2, an NPN bipolar transistor 3, and an LPNP transistor 5 are now formed in the semiconductor base 10, and a BiCMOS semiconductor device as shown in FIGS. 9A and 9B. Is obtained.
    [251] As in the first embodiment, the above-described second embodiment provides the following effects.
    [252] The insulating film 28 and the polysilicon film 30 protect the surface of the N-type epitaxial layer 13 of the LPNP transistor 5 from damage due to reactive ion etching.
    [253] The anti-reflection film 31 formed on the polysilicon film 30 prevents the pattern of the resist film forming the polysilicon film 30 from changing. In addition, this protects the polysilicon film 30 from the ingress of impurities by ion implantation for forming the emitter region / collector region.
    [254] The LPNP transistor 5 has an N-type polysilicon film 30 having a base lead configured to be connected to the silicon surface of the N-type polysilicon film 30 through the opening of the insulating film 28. The region 26B connected to the base may be formed by diffusing N-type impurities from the N-type polysilicon film 30 to the semiconductor base 10 at the portion connected to the base. Thus, it is possible to arrange the part connected to the base between the emitter and the collector. This reduces the area occupied by the emitter, the base, and the collector.
    [255] The cell size is smaller compared to the LPNP transistor 4 shown in FIG. Thus, the resulting LPNP transistor 5 has a small excitation capacity.
    [256] Since the base lead of the LPNP transistor 5 is configured in the same manner as the portion connected to the emitter of the NPN transistor 3, it can be formed in the same step at the same time as the portion connected to the emitter of the NPN transistor 3. . This allows the cell size to be reduced without increasing the number of fabrication steps.
    [257] Forming an opening 29 in the silicon oxide film 28 for the portion connected to the emitter of the NPN transistor 3 forms an opening 51 for the portion connected to the base of the LPNP transistor 5. Can be run concurrently with the steps. In this way, the opening 51 is filled to thereby form the N-type polysilicon film 30, and the region 26B connected to the base is formed by diffusing the N-type impurities from the N-type polysilicon film 30. It is also possible to reduce the area occupied by the emitter, the base, and the collector.
    [258] The cell size of the LPNP transistor 5 can be reduced (so the device size can be much smaller). This gives a higher integration BiCMOS semiconductor device with LPNP transistor 5.
    [259] The second embodiment is intended for a BiCMOS semiconductor device in which the LPNP transistor 5 is formed with the MOS transistors 1 and 2 in the same semiconductor base 10. However, the present invention is not limited to this BiCMOS semiconductor device.
    [260] The structure of the LPNP transistor 5 shown in FIG. 10B can also be applied to a bipolar semiconductor device in which no MOS transistor is formed. In this case, it is also possible to reduce the area occupied by the LPNP transistor 5 and to increase the degree of integration of the bipolar semiconductor device.
    [261] In the above embodiment, the PNP type transistor is referred to as a lateral bipolar transistor; However, the present invention can be equally applied to NPN type lateral bipolar transistors.
    [262] The invention is not limited to the embodiment described above. Various changes and modifications can be made in the present invention without departing from its intent and scope.
    [263] A semiconductor device having a lateral bipolar transistor has a small cell size for the lateral bipolar transistor, and thus has a small excitation capacity. In fabrication, the electrode layer connected to the base can be used for self alignment to form emitter regions and collector regions on both sides of the base region. Thus, it is possible to form the emitter region, the base region, and the collector region close together to reduce the cell size.
    [264] The resulting lateral bipolar transistor has a smaller size, which enables higher integration of the semiconductor device.
    [265] In a semiconductor device composed of a lateral bipolar transistor and a MOS transistor, when etching is performed to form side walls of the MOS transistor in the insulating film, the surface of the base region, which is an active region of the lateral bipolar transistor, is protected from damage by the insulating film. Is produced in a way. Thus, it is possible to prevent the low current amplification coefficient h FE from decreasing due to the increase in surface recombination current, and to improve the characteristic characteristics of the lateral bipolar transistor. This improves the reliability of the semiconductor device.
    [266] If the same insulating film is used to form sidewalls in the gate electrode of the MOS transistor and to form an insulating film in the base region of the MOS transistor, it is possible to form them simultaneously in the same step. This makes it possible to reduce the number of manufacturing steps.
    [267] The antireflection film formed on the polysilicon film prevents the pattern from changing due to exposure. This also prevents the impurity concentration from changing due to the ingress of impurities during ion implantation in the polysilicon film. This allows a certain level of impurity concentration to be maintained in the region formed by doping the surface of the semiconductor substrate with impurities from the polysilicon film.
    权利要求:
    Claims (11)
    [1" claim-type="Currently amended] In a semiconductor device having lateral bipolar transistors formed on a semiconductor base:
    An opening is formed in the base connection portion of the lateral bipolar transistor in the insulating film on the semiconductor base, and the electrode of the base connection portion is connected to the semiconductor base through the opening and emitter and collector ( and cover the base region between the collectors.
    [2" claim-type="Currently amended] The method of claim 1,
    The semiconductor device is characterized in that vertical bipolar transistors are additionally formed on the semiconductor base and the electrodes of the base connection portion covering the base region of the lateral bipolar transistor and the vertical transistors. And the emitter electrode is formed from a common layer.
    [3" claim-type="Currently amended] The method of claim 1,
    And the semiconductor device is configured such that an antireflection film is formed on an electrode layer with respect to the base connection portion.
    [4" claim-type="Currently amended] Transverse bipolar transistors and MOS transistors are formed in a common semiconductor base, and sidewalls on the gate electrode of the MOS transistor and an insulating film covering the base region of the base connection portion of the lateral bipolar transistor are formed of a common insulating film. A semiconductor device, characterized in that.
    [5" claim-type="Currently amended] The method of claim 4, wherein
    In the semiconductor device, an electrode layer of the base connection portion in the base connection portion of the lateral bipolar transistor is connected to the semiconductor base through an opening formed in the insulating film of the semiconductor base, and the base region between the emitter and the collector is connected. A semiconductor device configured to cover.
    [6" claim-type="Currently amended] The method of claim 4, wherein
    The semiconductor device is a semiconductor configured such that vertical bipolar transistors are additionally formed on a semiconductor base, and an electrode layer of the base connection portion covering the base region and an emitter electrode of the vertical transistor are formed from a common layer. device.
    [7" claim-type="Currently amended] The method of claim 4, wherein
    And the semiconductor device is configured such that an antireflection film is formed on an electrode layer for the base connection portion.
    [8" claim-type="Currently amended] A method of fabricating a semiconductor device having MOS transistors and lateral bipolar transistors formed on a common semiconductor base:
    Forming a gate electrode of the MOS transistor;
    Forming an insulating film on the entire surface,
    Forming a layer covering the base region between the emitter and the collector of the lateral bipolar transistor and later acting as a mask, and
    Etching the insulating film, thereby forming sidewalls for the gate electrode.
    [9" claim-type="Currently amended] The method of claim 8,
    The step of forming a layer to be a mask layer further comprises forming an electrode layer for the base connection portion of the lateral bipolar transistor.
    [10" claim-type="Currently amended] The method of claim 8,
    Introducing an impurity, thereby forming an emitter region and a collector region of said lateral bipolar transistor by a self-alignment process using said layer as a mask; How to make.
    [11" claim-type="Currently amended] The method of claim 8,
    And forming an antireflection film as a mask on the uppermost layer of the layer, and then introducing impurities to thereby form the emitter region and the collector region of the lateral bipolar transistor.
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    同族专利:
    公开号 | 公开日
    US20020048873A1|2002-04-25|
    JP2002026033A|2002-01-25|
    KR100818535B1|2008-04-01|
    JP4951807B2|2012-06-13|
    US6730557B2|2004-05-04|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    2000-07-11|Priority to JPJP-P-2000-00210259
    2000-07-11|Priority to JP2000210259A
    2001-07-11|Application filed by 이데이 노부유끼, 소니 가부시끼 가이샤
    2002-01-19|Publication of KR20020006470A
    2008-04-01|Application granted
    2008-04-01|Publication of KR100818535B1
    优先权:
    申请号 | 申请日 | 专利标题
    JPJP-P-2000-00210259|2000-07-11|
    JP2000210259A|JP4951807B2|2000-07-11|2000-07-11|Semiconductor device and manufacturing method thereof|
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